1. Field of the Invention
The present invention is related to charge-coupled devices and, more particularly, to charge-coupled devices having low transfer times.
2. Description of the Prior Art
In the prior art, charge-coupled devices (CCD's) has been developed to provide for the controlled transfer of charge carriers in response to clocking signals. Briefly, prior art CCD's are comprised of a charge injection structure, a charge clocking structure, and a charge output structure. The charge clocking structure includes an insulation layer interfaced with a semiconductor wafer. Gating electrodes, attached to the surface of the insulation layer that is oppositely disposed from the semiconductor-insulation interface, are responsive to clocking signals to provide an electric field which establishes a space charge region in the semiconductor wafer. The timing and magnitude of the clocking signals are such that the profile of the space charge region forms potential wells of controlled depth and width, the wells being caused to move laterally along the semiconductor-insulator interface in accordance with the timing of the clocking signals. Signal charge carriers that are present in the semiconductor wafer are located in regions having the lowest potential energy so that the signal charge carriers are laterally transported along the semiconductor-insulator interface in accordance with the progression of the local potential well minima generated by the clocking signals on the electrodes.
Change carriers are introduced in the semiconductor by the charge injection structure which can have any of a variety of well-known mechanisms. Usually, the manner in which the charge carriers are introduced is dependent on the application of the CCD. For example, when the CCD is to be used as a delay line, the charge carriers are typically introduced electrically through a diode or an ohmic contact to the semiconductor. But, when the CCD is to be used as a light sensitive element, the charge carriers are introduced by photogenerating charge carriers directly within the CCD potential wells with photons. Similarly to the charge injection structure, the charge output or readout structure is dependent on the intended use of the CCD. Any of several well-known mechanisms may be employed in a particular application.
As explained previously with regard to the charge clocking structure, the signal charge carriers in the semi-conductor wafer are contained in the potential wells having the lowest local potential energy and are transported laterally along the semiconductor insulator interface as the position of the local potential well minima are laterally shifted in accordance with changes in the voltage applied to the gating electrodes. In the prior art CCD's, there are three transport mechanisms which cause the signal charge carriers to follow the potential wells through a lateral change in position. These mechanisms include: a self-induced drift field; a fringe drift field; and thermal diffusion. More specifically, the self-induced drift field results from the common polarity of the charge carriers and their proximity within the potential wells. That is, the common polarity charge carriers repelled one another and therefore tended to move the charge carriers in a lateral direction. The fringe drift field transport mechanism is the result of an overlap of the electric field provided by one electrode and the higher electric field provided by an adjacent electrode such that the charge carrier tends to be drawn toward the electrode having the stronger electric field. The thermal diffusion transport mechanism is produced by the thermal motion of the signal charge carriers. This carrier transport mechanism became most prominent at the end of each transfer cycle. Although it is comparatively slow, it is the chief transfer agent when self-induced drift has ceased and fringing fields do not reach sufficiently far under adjacent gates.
In the prior art, CCD's were often required in mechanisms which demanded high operating speed for the CCD. Therefore, there were in the prior art, further improvements made in the basic CCD to lower the required transfer time of charge carriers between adjacent electrodes and thereby increase the operational frequency of the CCD. In one improvement, the CCD was provided with a higher number of clocking signals which were applied to adjacent electrodes. The relative magnitudes of the clocking signals were such that they established a stepped space charge region in the semiconductor wafer which produced a potential profile with several levels of potential energy within the potential well region containing the charge carriers. Although this modification afforded some improvement in the transfer time of the CCD, the transport mechanisms remained, basically, the same. Also, in these prior art CCD's, the CCD conduction path was adjacent to the semiconductor-insulator interface so that surface states located at the interface imposed certain limitations on the CCD performance. Specifically, the surface states impaired the efficiency of the CCD's by trapping and/or scattering charge as it was transferred between adjacent CCD wells. Furthermore, the surface states acted as scattering centers which reduced the mobility of charge in the CCD and, therefore, the charge transfer speed of the CCD. Consequently, the need for a greater improvement in the transfer times remained.
To eliminate the undesirable interaction between the charge and the surface states at the semiconductor-insulator interface, the charge conduction path was located away from the interface. This class of CCD's is generally referred to as buried channel CCD's (BCCD). Locating the charge transport path inside the semiconductor increased the mobility of the charge carrier and reduced the number of trapping and scattering sites with which the charge signals would interact. Also, the location of the charge transport path away from the semiconductor-insulator interface in the BCCD's, magnified the influence of the fringing drift field on the charge transport between adjacent potential wells of the buried channel. Because the transport channel was located farther from the clocking electrodes in the BCCD's, the screening effect of adjacent clocking electrodes decreased, thereby increasing the fringing drift field effect. However, with larger amounts of charge in the buried channel, interaction between the surface and the charge in the buried channel occurred. Because the charge transport channel was physically disposed further from the clocking electrodes, the charge handling capability of the BCCD was reduced or, alternatively, a higher voltage was required for the clocking signals.
In order to move the buried charge transport channel further from the clocking electrodes to further magnify the fringing drift field effect and to minimize the interaction of the charge in the buried channel with the surface, a modification of BCCD's was developed known as the peristaltic CCD (PCCD). Similar to the BCCD's, the PCCD's provided a charge transport channel by reverse biasing a diode junction. To increase the charge handling capability of the PCCD, one of the semiconductor materials of the diode junction was given a graded impurity concentration. The gradient in impurity concentration in the PCCD's was such that most of the charge was located near the semiconductor-insulator interface while a smaller amount of charge was located at the diode junction. This charge distribution profile afforded increased charge handling capability by confining the charge near the clocking electrodes. The non-uniform impurity concentration of the semiconductor wafer also had the effect of concentrating the charge carriers to one side of the potential wells and in aiding them in their lateral transport as the position of the potential changed, thereby further improving the transfer times between adjacent potential wells of the PCCD. Although the modification of the BCCD's which resulted in the PCCD's had the effect of improving transfer times due to the non-uniform impurity concentration of the semiconductor under each electrode, the control of the impurity concentration over such small tolerances made these prior art devices relatively difficult to manufacture.
The limitation in the operational frequency of the prior art CCD's was inherent in the transfer mechanisms upon which their operation was based. This limitation was most severe in surface and buried channel CCD. Therefore, there remained a need for a CCD which would operate at frequencies several orders of magnitude higher than the frequencies obtainable by prior art surface and buried channel CCD's while retaining the structural simplicity of the surface channel devices.